In many important network applications there is a need to synchronize clocks running at various nodes in a computer network. Such synchronization of clocks over the network is generally achieved by transmitting data packets containing timestamps to the clocks being synchronized. The IEEE 1588 protocol standardized by the Institute of Electrical and Electronic Engineers (IEEE) is one protocol that can be used to synchronize clocks over a network. The IEEE 1588 protocol is designed to measure the time taken by data packets containing timestamps to travel across a communication medium (typically the Ethernet) and the time taken to transport these data packets over intermediate nodes in the network that may have variable buffering delays. However, after these data packets containing timestamps reach the receiver of a destination node there may be additional delays between the time instance when a data packet is received at the pins of the receiver and the time instance when the processing circuitry of the receiver reads the timestamp contained in the data packet. Typical implementations of the IEEE 1588 protocol do not account for these additional delays precisely.
There may be several sources of potential delay uncertainty between the time instance when a data packet is received at the pins of the receiver and the time instance when the processing circuitry of the receiver reads the timestamp contained in the data packet. For example, receivers in 10G-baseR Ethernet networks may include a deserializer circuit, a gearbox circuit, a word-aligner circuit, and/or a first-in-first-out (FIFO) queue circuit. Each of these circuits may potentially introduce delays as a data packet traverses that circuit.
Some 10G-baseR Ethernet networks do not need to resolve the delay uncertainties discussed above. Other 10G-baseR Ethernet networks make considerable effort to timestamp data packets on the pin-side of the gearbox circuit so that the receiver's processing circuitry can determine the delay introduced by the gearbox circuit. Yet other 10G-baseR Ethernet networks mark all data packets that are potentially IEEE 1588 protocol data packets at the pin-side of the gearbox circuit, create a special deterministic latency path that eventually feeds data packets to the receiver's processing circuitry, and finally re-tie each data packet from the special path. The latter two techniques for determining the delays introduced by various receiver circuitries are invasive and sometimes incompatible with existing receiver architectures.